UGC NET Computer Science 2018 Previous Year Questions (PYQs) – Page 2 of 3

For equation $(i)$,

$wx+w(\overline{x}+y)+x(\overline{x}+y)$

$=wx+w\overline{x}+wy+x\overline{x}+xy$

Since,

$x\overline{x}=0$

So,

$=wx+w\overline{x}+wy+xy$

$=w(x+\overline{x})+wy+xy$

$=w+wy+xy$

$=w+xy$

But the right side is

$x+wy$

Since $w+xy$ is not always equal to $x+wy$, equation $(i)$ is false.

Now, for equation $(ii)$,

$(w\overline{x}(y+x\overline{z})+\overline{w}\overline{x})y$

$=(w\overline{x}y+w\overline{x}x\overline{z}+\overline{w}\overline{x})y$

Since,

$\overline{x}x=0$

So,

$=(w\overline{x}y+\overline{w}\overline{x})y$

$=w\overline{x}y+\overline{w}\overline{x}y$

$=\overline{x}y(w+\overline{w})$

$=\overline{x}y$

So, equation $(ii)$ is true.

Therefore, $(i)$ is false and $(ii)$ is true.

Using Kruskal's algorithm, we select edges in increasing order of weights, without forming a cycle.

From the graph, the selected edge weights are:

$1,1,1,2,2,2,3,4$

Since the graph has $9$ vertices, the minimum spanning tree must have

$9-1=8$ edges.

Now, total weight of MST is

$1+1+1+2+2+2+3+4$

$=16$

Therefore, the weight of the minimum spanning tree is

$16$

Statement $(i)$ is false.

Self-relocating code is mainly supported by relative addressing, not by auto increment addressing.

Statement $(ii)$ is false.

Auto increment addressing does not necessarily require an additional ALU. The increment can be handled by the processor hardware.

Statement $(iii)$ is true.

In auto increment addressing mode, the register is incremented according to the size of the data item accessed.

For example, if byte is accessed, increment may be $1$. If word is accessed, increment may be more.

Therefore, only statement $(iii)$ is true.

Memory size is

$256K=256\times 1024=2^8\times 2^{10}=2^{18}$ words

So, address part requires

$18$ bits

Number of registers is

$64=2^6$

So, register code requires

$6$ bits

Instruction size is

$32$ bits

Indirect bit requires

$1$ bit

So, operation code bits are

$32-1-6-18=7$

Therefore, operation code, register code and address part are

$7,6,18$

Given,

$AL=153$

Binary form of $153$ is

$10011001$

The instruction NEG AL performs two's complement.

So,

Two's complement of $10011001$ is

$01100111$

Therefore,

$AL=01100111$

Since the operand is non-zero, Carry Flag is set.

So,

$CF=1$

The result $01100111$ has most significant bit $0$.

So, Sign Flag is

$SF=0$

Given number is

$-40.1$

Since the number is negative, sign bit is

$1$

Now,

$40.1$ in binary is approximately

$101000.000110011001100110\ldots$

Normalize it:

$101000.000110011001100110\ldots=1.01000000110011001100110\ldots\times 2^5$

So, exponent is

$5$

IEEE-754 single precision bias is

$127$

Biased exponent is

$127+5=132$

Binary of $132$ is

$10000100$

Mantissa bits are

$01000000110011001100110$

So, IEEE-754 representation is

$1\ 10000100\ 01000000110011001100110$

This gives hexadecimal form:

$\text{C2206666}$

Therefore, the answer is

$\text{0xC2206666}$

Hence, the correct answer is Option 1.

Gate $1$ is a NAND gate with inputs $A$ and $B$.

So, output of gate $1$ is

$\overline{AB}$

Now, gate $2$ is a NOR gate.

Its inputs are $\overline{A}$ and $B$.

So, output of gate $2$ is

$\overline{\overline{A}+B}$

Using De Morgan's law,

$\overline{\overline{A}+B}=A\overline{B}$

Now, gate $3$ is also a NOR gate.

Its inputs are $\overline{AB}$ and $A\overline{B}$.

So,

$Y=\overline{\overline{AB}+A\overline{B}}$

Now,

$\overline{AB}=\overline{A}+\overline{B}$

Therefore,

$Y=\overline{\overline{A}+\overline{B}+A\overline{B}}$

Since $\overline{B}+A\overline{B}=\overline{B}$,

$Y=\overline{\overline{A}+\overline{B}}$

Using De Morgan's law,

$Y=AB$

Number of surfaces is

$32=2^5$

So, surface number needs $5$ bits.

Number of tracks is

$64=2^6$

So, track number needs $6$ bits.

Number of sectors is

$512=2^9$

So, sector number needs $9$ bits.

Therefore, total bits required are

$5+6+9=20$

evel $1$ hit rate $=0.7$

Level $2$ hit rate $=0.8$

Level $1$ access time $=0.5$ ns

Level $2$ access time $=5$ ns

Main memory access time $=100$ ns

Average access time is

$0.7(0.5)+0.3[0.8(5)+0.2(100)]$

$=0.35+0.3[4+20]$

$=0.35+0.3(24)$

$=0.35+7.2$

$=7.55$ ns

Statement $(i)$ is not a standard sufficient condition for Hamiltonian graph.

By Dirac's theorem, the sufficient condition is

$\deg(v)\geq \dfrac{n}{2}$

for every vertex $v$.

So, statement $(i)$ is false.

Statement $(ii)$ is true by Ore's theorem.

Ore's theorem says that if for every pair of non-adjacent vertices $v$ and $w$,

$\deg(v)+\deg(w)\geq n$

then the graph is Hamiltonian.

Statement $(iii)$ is not the standard sufficient condition here.

Therefore, only statement $(ii)$ is correct.